The invention relates to a semiconductor device, and more particularly to a substrate for performing a burn-in test of integrated circuit chips (IC chips) and a method of manufacturing a good die array utilizing the substrate.
Standard integrated circuit chips, in general, are subjected to various tests in order to determine the reliability of the chips before distributing the chips for use. Briefly, there are two important reliability tests: one is an electrical characteristic test in which all input and output terminals are connected to a test signal generator to verify the transferring characteristics between the signals coming in and out at the terminals; the other is a burn-in test in which a given chip is exposed to overstress conditions of higher than normal operating temperatures and voltages to verify its lifetime and to detect defects.
As an example, the burn-in test for a dynamic random access memory chip has appreciated as a useful method to verify the reliability of memory circuit elements such as memory cells and signal lines. During the burn-in test, defects latent in a dynamic random access memory chip result in the destruction of gate oxide films of MOS transistors and shortening between multi-leveled conduction layers. These defective chips are abandoned as inferior and non-defective chips are selected as a known good die instead.
In such a burn-in test, the defective chips abandoned as inferior are about 5% to 10% of the tested chips. Therefore, since the defective chips are already packaged, the conventional technologies for fabricating the known good die require the use of many materials and the unwanted investment of unnecessary cost.